High Density Terrace Integration And Transistor Devices Application Of Ultrathin Silicon Nanowires

In the age of Internet and information,human’s daily life and work increasingly rely on the visualization and pictorial interaction of information data,which makes information exchange more vivid and effective.Therefore,Flat Panel Display(FPD)equipment plays an increasingly important role in daily life.Meanwhile,the display industry has been pursuing key technical indicators such as high quality,large size,high resolution and so on,which are related to cost and competitiveness.In the FPD devices,the Thin Film Transistor(TFT)driving is an extremely important technical link.However,traditional amorphous silicon(a-Si)TFT driving is limited by many defects,low mobility,poor stability and other technical problems,it has been difficult to meet the application requirements of the new type display such as super large screen,high resolution and flexible display.Seeking better TFT channel materials to prepare driving circuits with good electrical properties has been an important research direction.On the other hand,traditional silicon-based materials have become industry preference due to the advantages of low cost and the technology maturation,and quasi-one-dimensional silicon nanowires(Si NWs)are ideal channels for constructing high performance nanoelectronics and sensors.Achieving a rather thin diameter is the key to maximize the gate-channel capacitive coupling and achieve rapid on/off current switching.However,fabricating such ultrathin Si NW channels at pre-known locations can only be accomplished via high precision top-down electron beam lithography and etching so far,which are difficult to apply for large area electronics,such as FPD.In contrast,bottom-up self-assembled catalytic growth can produce high-yield tiny nanowires at relatively low temperatures,with the aid of metallic catalyst nano-droplets.Though a number of nanoelectronics has been fabricated based on the Si NWs grown via the traditional vapor-liquid-solid(VLS)mechanism,the challenges are the difficulties in locating and integration of vertical nanowire structure,which leads to the complexity and the high cost of device preparation.At the same time,in order to obtain high driving current and utilize the substrate area effectively,nanowire high-density stacking has become an important research route and trend.This paper mainly revolves around a new kind of Si NWs self-assembled growth technology called in-plane solid-liquid-solid(IPSLS)mechanism to start some exploratory work.This planar self-positioning nanowire array is able to serve as conducting channel to fabricate high performance TFT.Meanwhile,without using any high resolution lithography equipment,the combination of alternating step erosion technology and IPSLS growth mechanism enabled to explore the limits of spacing and diameters of stacked Si NWs and the growth stability.The use of tighter and denser terraces helped to increase the integration density of Si NWs by 6 times,and the assembled transistors also show an excellent electrical property.Finally,considering the demand of flexible electronic devices,we further explore the technological process of fabricating transistor devices under low temperature conditions.Next follows the main work and innovation points of this paper:1.SiNWs array with uniform diameter and high yield is acquired based on IPSLS mechanism and served as conducting channel to fabricate high performance transistors.Some process parameters of the fabrication procedures are also optimized and improved to provide an experimental basis for large scale application of Si NWs.2.Combine step erosion technology and IPSLS growth mechanism to investigate the confinement effect on nanowire growth of compact steps.Further,by controlling the growth parameter,the integration density of Si NWs is increased by 6 times,and the minimum spacing and diameter are lowered to 80 nm and 27 nm,respectively.Also,the assembled transistors achieve a high Ion/Ioff current ratio ~107,low leakage current of ~0.3 p A and steep subthreshold swing of 220 m V/dec,which indicates a promising route to apply for large area advanced electronics.3.Out of the consideration of polymer substrates and flexible electronics,replacing traditional high temperature process with solution-based alternating treatment to passivate the defect states on Si NWs during the fabrication of transistors.This new process also enables a good device with an ideal on/off current ratio excess 105 and low leakage current of ~0.1 p A,which is promising to fabricate transistor array on flexible substrates under low temperature.