Coarse Grained Reconfigurable Architecture Simulator Design And Power Efficiency Optimization

With the emergence of new applications,it is more and more difficult for computing architectures,such as application specific integrated circuit,general purpose processors,field programmable gate arrays to meet people's demand.However,in recent years,coarse-grained reconfigurable architectures have gained increasing attention due to their flexible configurability and significant power efficiency.As one of the characteristics of the coarse-grained reconfigurable architecture,the extensive configurability makes the architecture have a wide design space and can flexibly meet the needs of different applications,but it also increases the design's difficulty.Architects often need to model different structures of the design early in the design process,so having convenient modeling and simulation tools is especially important.Coarse-grained reconfigurable architecture simulators need to meet the requirements of high-level abstract modeling,dynamically configurable architecture parameters,and convenient system-level integration.Aiming at these requirements,this paper proposes a design scheme of coarse-grained reconfigurable architecture simulator based on Gem5,which is highly modular,discrete-event driven and system-level testing.In this paper,a simulator implementation of a specific heterogeneous coarse-grained reconfigurable architecture is taken as an example to describe the modeling design process based on Gem5 and the system-level integration scheme,aiming to provide a general,fast and easy system-level integration design idea for the modeling work of coarse-grained reconfigurable architectures.In the process of analyzing the performance results of the simulator simulation and the power consumption results of RTL simulation,we found that the configuration cost of the coarse-grained reconfigurable architecture instruction was too high.For this reason,this paper puts forward an instruction compression scheme based on similarity.This scheme makes use of the obvious similarity between the coarse-grained reconfigurable architecture instructions found in practice to realize the compression of the instructions.This scheme can significantly reduce the instruction configuration cost of coarse-grained reconfigurable architectures under the premise of less performance loss,so as to finally achieve the goal of improving the architecture power efficiency.The experimental results show that compared with the two baseline architectures,our scheme has improved the area efficiency by 36% and 181%,and the power efficiency by 33% and 118% respectively.