Implementation And Verification Of HDLC Protocol Parallel Decoder

In digital communication systems,the HDLC protocol is widely used on the data link layer.Its advantage is that it can easily realize the transparent transmission of data and meet the requirements of large bandwidth,high reliability,and strong real-time performance of the data link.An encoder and a decoder are needed to implement HDLC protocol communication.There are two implementation methods: software and hardware.In high-speed data communication applications,hardware methods are usually used to implement the HDLC protocol.On the FPGA chip platform,the HDLC decoder designed using the verilog language has strong modifiability,and can be flexibly applied to various HDLC protocol communication occasions.This method has a very economic cost and has great research value.In the structure of the HDLC data frame,the error check code at the end selects the CRC-16 check method.Use the recursion method for the parallel 8-bit input data to get the logic code of the data update in the CRC register.Compared with the serial CRC check method and the CRC check method based on the look-up table method,the advantage of the recursive method is that the data processing speed is faster than the bit-wise serial calculation method,and the storage space is smaller than the look-up table method,which is conducive to miniaturization,Fast hardware implementation.After that,a verification platform based on system verilog was built for this decoder design.After running the test code,it can be known from the waveform diagram that the HDLC decoder circuit implemented by this method is feasible and has great application value..The HDLC decoder module implemented in this article is a miniaturized and fast hardware implementation that can be used by the HDLC protocol receiver in high-speed data communication applications,and has strong practical value.What is worthy of improvement in the work is that due to time and energy,the verification platform built is not complete enough,there is no functional module that realizes the automatic comparison results,and the verification automation is not fully realized;the designed decoder does not have an additional module for reporting and warning abnormal data.design.These deficiencies need to be perfected in the future.