Research On Fully Integrated Fractional-N Frequency Synthesizer

With the rise of Internet of Things,Narrowband Internet of Things technology in wireless communication system has emerged and become a key for connecting everything to the Internet.Frequency synthesizers,as a center part in a wireless communication system,provide high-quality local oscillator signals.The performance of the frequency synthesizer determines whether the whole transceiver system works effectively,so its study is crucial.This thesis designs a fractional phase locked loop frequency synthesizer used in an RF transceiver chip for narrowband Internet of Things.Based on the investigation on the development of narrowband Internet of Things and the technology status of frequency synthesizer within the country and abroad,various circuit blocks of the phase locked loop frequency synthesizer are studied.First,the architecture and working process of the phase-locked loop frequency synthesizer system is described,followed by system modeling and simulation using Simulink tools,and then investigating the relationship between voltage ripple and system spurs.An improved phase-locked loop frequency synthesizer system is then proposed,by adding a tracking feedback loop over the original structure which dynamically tracking the signal after frequency division and provides feeding back,yielding lower the spurs and faster locking time.Understanding the non-ideal characteristics of each circuit block,this thesis presented a phase frequency detector that can avoid dead zone,a charge pump with low current mismatch and adjustable charging and discharging current,an inductance capacitor voltage controlled oscillator with 16 output frequency bands and the covering rate reached 58.3 percent,a multiple modulus frequency divider whose frequency division ratio was 64-127,and a Sigma-delta modulator with 24 bit MASH1-1-1structure.The circuit design is based on UMC55 nm CMOS technology.The input reference frequency was 19.2MHz and the output frequency range was 699 MHz to960MHz and 1800 MHz to 2150 MHz.Under 1.8V voltage,the simulation showed when the lock frequency was 1904.68 MHz,the lock time was less than 7.95?s,the reference spurs was-54.36 d B,and the power dissipation was 7.45 m W.The performance figures of this design can meet the demand for the NB-Io T RF transceiver system.