No Phase Truncation Error Of Dds Design Based On Fpga

In the resent twenty years, along with the development of micro-electronics technology, higher demands on the stability and accuracy of the signal frequency increase.In communications,meter,radar,aerospace and other applications, stable and accurate frequency is required during a certain range frequency,at the same time traditional oscillator can not meet the demands.But the frequency synthesizer technology emergence,develope fast and is been widely used.At present, the commonly used frequency synthesizer technology includes:direct frequency synthesizer technology, indirect frequency synthesizer, direct digital frequency synthesis (DDS). DDS uses all-digital technology, and has the compositions of the phase accumulator, ROM lookup table, DAC and low-pass filter. Because of the all-digital structure,DDS has many advantages,such as higher frequency resolution, the more output frequency point,fast frequency conversio. DDS The excellent performances which other frequency synthesizer technology don’t have, and also the created all-digital structure for the frequency synthesizer to provide an important design style,thus the DDS is also known as third-generation frequency synthesizer.Firstly this article introduced the principle of DDS and the structure of the system, summarized the advantages and the problem of low spurious reduction. Then,this article carried out research on the issue of DDS spurious,analysd the ideal DDS, calculated and analyzed the phase truncation error and amplitude quantization error,introduced spurious spectral conversion of non-ideality in the DAC conducted a qualitative analysis.On this basis, a few of the more practical spurious reduction methods has been given,such as sine symmetry Improvement Act, Sunderland structure, jitter injection method.Then, based on the previous analysis, put forward by improved ROM structure and lookup table mechanism without phase truncation error of DDS design.To analysis of its feasibility,modeled and simulated the improve shceme. Finally, based on the FPGA design of the none phase truncation error DDS which phase accumulator is24bits, the amplitude quantization bits to10. And simulated and test output data of the the DDS in the system clock frequency of50MHz, frequency control word for671088, output frequency of2MHz。Simulation results show that the maximum spurious noise strength is-80dB, design of none phase truncation error of DDS basically eliminates the phase truncation error, greatly reduces the spurious noise.