| One of the critical aspects of semiconductor fabrication is the patterning of multiple design layers onto silicon wafers. Since 180nm processes came online, the semiconductor industry has operated under conditions in which the critical features are smaller than the wavelength of light used during the patterning process. Such sub-wavelength conditions present many challenges because topology, rather than feature width and space, defines the yield characteristics of the devices.; Pattern variability can contribute as much as 80% of the total timing margins defined by traditional SPICE corner models. Because feature variability is undesirable from electrical considerations, this work proposes a physical design verification methodology that emphasizes pattern robustness to process variations. This new method is based on a framework composed of manufacturability objects, operators and guidelines, which permits the definition of a scoring system ranking the manufacturing process and the manufacturability of the designs.; This framework is intended to alleviate circuit design and verification challenges and it based on three new concepts: the first relates to compact process model requirements. The second involves the definition of a new design object, called pv-Band, which reflects layout sensitivity to process variations. The third is the specification of two manufacturability metrics that, when optimized, can improve yield by accounting layout sensitivities across multiple design levels (e.g., Active, polysilicon, contact, metal 1, etc.).; By integrating these new concepts (process models, pv-Bands and manufacturability metrics) with existing knowledge, this work moves forward the state-of-the-art of physical design and verification of integrated circuits subject to sub-wavelength effects. |
