High-speed Backplane Ethernet Fec Technology

The capacity and distance of data transmission is increasing along with the developing of internet communication especially Ethernet. But because of of noisy and non-linear effection, the high-speed and long-distance transmission is restricted. In order to be seasoned with large capacity and high QoS it is necessary to use FEC in internet communication.There are two error-control technique in digitial communication:ARQ (Automatic Repeat reQuest) and FEC(Forward Error Correction).There are two error-control technique in digitial communication:ARQ (Automatic Repeat reQuest) and FEC(Forward Error Correction).When there is a high bit error rate, the repetitive TXD will cut down the efficiency and conduce network block. Modern network will not use ARQ when fiber is used widely because ARQ will be the bottle-neck.FEC which is channel encoding is implemented by inputing data into FEC encoder to produce special codes which have error-correcting capability. In the receiving end, the FEC decoder will decode the received data. If there are some error-bits in the data when transferring and the error-bits within the error correcting capability of codes, the decoder will find the error-bits and correct them.The application and implementing of FEC in high-speed network will be introduced mainly.Channel encoding is designed for better data transfer quality in communication systems. Becaude of noise and interference, data will have error when transferring. There are two error types: burst-error and random-error.In many high-speed channels, the data have random error(have error separately) with a low probability. But the error-bits will arose error bits in the adjacent data bits with a high probability. Such as 10G Backplane Ethernet, the probability of having an error bit is10-8-10-12,but the probability of attracting the adjacent error bits is 10-3or more. So burst-error is the main error type in many high-speed channels.The encoding and decoding in this paper is mainly designed for burst-error. In modern communication, the channel encoding is mainly implemented by cyclic codes like RS,BCH codes. So the corresponding decoding is cyclic. But in many channels, like backplane channel, the protocol prescribes the codes are common binary cyclic codes. Comparing with RS and BCH code, decoding binary cyclic codes is not unique. Generally speaking, it is implemented using Linear Feedback Shift Registers(LFSR). Such decoding schemes with LFSR use sequential logic and are generally easy to implement and require less hardware. However, such sequential decoding schemes are not suitable for modern high-speed channels that demand high-speed parallel decoding. Data storage and propagation delay are the main limitation.Parallel encoding and decoding cyclic codes will be introduced in this paper.Parallel encoding and decoding cyclic codes are designed by taking the high-speed Backplane Ethernet channel for example under the condition of high-speed and large data communication. This paper comprise two parts, one is about existing sequential encoding cyclic codes and the designed parallel encoding cyclic codes. The other is about existing sequential decoding cyclic codes and existing parallel decoding cyclic codes and deficiencies of their's. The designed parallel parallel error-trapping decoding cyclic burst error correcting codes will be introduced detailed。It is suitable for decoding any cyclic burst error correcting codes especially for long cyclic burst error correcting codes.