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Design Of Low Power RF Receiving Front-end For IoT

Posted on:2021-06-17Degree:MasterType:Thesis
Country:ChinaCandidate:X Y YangFull Text:PDF
GTID:2518306476960279Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
The development of the 5G technology and the Internet of things technology makes low-power wireless transceiver systems a hot spot for research,and the RF front-end is a key module in the RF receiving link.As the key module in the RF receiving link,the RF front-end determines its performance to a large extent,and it is also the main energy-consuming module.Reducing the power consumption under the premise of ensuring the performance of the RF front-end is important and has important scientific research value and engineering significance.In this thesis,a low-power RF front-end for Internet of things is designed,which achieves low-power design and low noise figure and high conversion gain to ensure the realization of high sensitivity of the RF receiver.An improved design of a current multiplexing low-noise amplifier with an adaptive bias circuit is proposed.Through the current multiplexing between the NMOS transconductor and the PMOS transconductor,a large equivalent input transconductance,high gain and low noise figure are obtained at low power consumption.Compared with the traditional current multiplexing low noise amplifier,there is no need to introduce multiple on-chip inductors,and the circuit performance is not affected by power supply voltage,temperature and process angle;A single-balanced passive mixer structure is adopted,and a self-biased push-pull transconductance amplifier is designed to obtain a large equivalent transconductance value and high linearity at low power consumption;The common-gate circuit based on the super source follower structure is used in the transimpedance stage,and a DC offset cancellation circuit that simulates a parallel negative feedback structure is designed to achieve suppression of the DC offset voltage.Based on the TSMC 55 nm RFCMOS process,the schematic and layout design are completed,and the tape-out is carried out after simulation verification.The simulation results show that under 1.2V supply voltage,the power consumption of the RF receiving front-end designed in this paper is 4.44 m W,while achieving a conversion gain of 32 d B and an input reflection coefficient of-16 d B.The entire RF receiver achieves a sensitivity of-104 d Bm and a noise figure of 6.5d B at power consumption of 10.5m W,reaching design requirements.
Keywords/Search Tags:RF front-end, low power consumption, current reusing, high sensitivity
PDF Full Text Request
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