1588 Time Synchronization Method Based On SPN

With the development and popularization of communication technology,the services provided by network communication also tend to be diversified and multimedia.Correspondingly,the demand for high-speed communication in the network is increasing.With the gradual improvement of network medium speed,the requirements of synchronization accuracy in the network are also gradually increased.Therefore,in terms of time synchronization,many time synchronization schemes have been proposed.In order to meet the clock synchronization requirements of different frequency systems and provide accurate clock synchronization services for the system,IEEE1588 time synchronization protocol is proposed to solve these problems.Compared with the traditional NTP clock protocol,IEEE1588 can provide more accurate timing service.In this paper,we first introduce the development of packet network,and focus on the architecture of sliced packet network and the application of Flex technology.Then it introduces the advantages of IEEE1588 time protocol over other protocols,analyzes the factors affecting time synchronization in 1588 time system,and proposes the method of asymmetric compensation in the system.The IEEE1588 time synchronization system in sliced network is designed.The work of this paper is as follows:1)This paper analyzes IEEE1588 time synchronization protocol,including the clock model,the implementation method of corresponding clock model,including the construction of time synchronization system,the implementation scheme of time synchronization operation,and the way of extracting time stamp.Aiming at the design and implementation of clock synchronization,the clock synchronization mode,asymmetric compensation mode,PTP frame format and timestamp processing mode are studied.2)This paper analyzes the time processing mode of the system,the message receiving and sending,time stamp processing,delay time calculation,transparent clock and correction domain processing in the event system.Finally,the asymmetric time delay in the system is compensated.3)In this paper,the design module and module structure are planned and designed.The Verilog code is implemented for each module and the whole design.Through the function division of the module,the writing of the module is simple and intuitive.4)Verify the design module,build a simulation platform,write incentives,so as to test the input and output of the module,and verify the sending and receiving of different messages in different scenarios.5)The design module is tested on FPGA and time synchronization performance is tested to verify the reliability of the design.