Research And Implementation Of DMA Transmission Based On RapidIO Of SoC

This project comes from a pre-research project of a chip company.It aims to design a high-performance SOC for the field of communication,which requires the realization of high-speed interconnection communication between boards.Rapid IO is the only international standard for embedded interconnection.With its high performance,high reliability,high bandwidth,low pin count and flexible structure,it has become the first choice for system interconnection in high-performance embedded field.Based on the above background,the So C design integrates GRIO(Generic Rapid IO Controller)based on the Rapid IO 2.2 protocol specification,and the single channel rate can reach 6.25 Gbaud,which is sufficient to meet the data transmission requirements of most communication applications.Meanwhile,considering the impact of mass data transmission on system performance,this design integrates a DMA controller inside RAB(Rapid IO-AXI Bridge)to reduce processor resource consumption and system performance loss.The main work of this thesis is to verify the system level protocol function of Rapid IO interface module from the bus driver software layer,ensuring that the design circuit is correct in function,and achieving the expected transmission performance.Firstly,this thesis deeply analyzes the basic contents of the Rapid IO protocol,including the Rapid IO architecture,transmission mechanism,request/response packet format,and some supported transaction types,laying a theoretical foundation for the design of the Rapid IO interface function module.Next,the design of GRIO and RAB are introduced comprehensively.The GRIO part focuses on the GRIO structure and the supported I / O transactions and packages.The RAB part mainly discusses the design of the RAB structure,configuration space access,and address mapping mechanism.And compares the difference between PIO operation mode and DMA operation mode,which triggered the importance of DMA technology.Then,the design of the DMA engine is described in detail,mainly introducing the read and write DMA data stream,DMA engine structure and DMA transfer mode.Finally,the function verification is carried out.The thesis describes the software configuration process for various operations in detail.Then,the simulation waveform is analyzed to confirm the correctness of the designed circuit function.After the test is passed in the simulation environment,the FPGA board is further carried out.Through the point-to-point test with Rapid IO soft IP core on the Xilinx zynq7000 zc706 development board,it shows that read/write bandwidth of DMA designed in this thesis can reach over 90% of the theoretical effective data bandwidth.