Design And Implementation Of General Signal Processing Platform Based On PCIe GEN3

In recent years,the fast development of signal processing and the improvement of packaging processes have enabled efficient processing of large data volumes.Especially in terms of artificial intelligence,the increasing bandwidth of signal processing makes traditional data buses unable to meet the requirements of large amounts of data and strong real-time performance.The PCIe bus is widely used as an I/O bus replacing traditional data transfer protocols such as ISA and PCI.It has developed to the third generation,and the fourth generation is about to leave the lab stage.However,the PCIe GEN2 protocol is currently the most commonly used in the industry.Due to the recent emergence of mature FPGA models supporting both the PCIe GEN3 protocol and DDR4 cache in the full range of production quantities of the Xilinx KU series FPGAs,a design scheme of a general signal processing platform based on PCIe GEN3 protocol is proposed.The design scheme can improve the existing signal processing capabilities and transmission speeds,realize twice the actual data bandwidth of the PCIe GEN2 protocol,and has good versatility and scalability.In terms of hardware design,the architecture of the current more flexible signal processing system is applied.The core FPGA signal processor,DDR4 cache module,and PCIe GEN3 high-speed interface are centralized on the carrier card.The FMC connector is used to match different expansion daughter cards.The signal rate of each module is around 10 Gbps.The specific PCB design requirements are put forward to improve signal integrity in light of actual conditions.In terms of software design,the DMA engine is designed for the PCIe GEN3 driver and practical application,which improved the bandwidth utilization.The DDR4 read/write engine is designed for practical applications to give full play to the performance of the DDR4 cache module.The actual test data is recorded and analyzed.