| Information security is gaining increasing importance in the current social life. Public key cryptosystems, such as RSA which is widely used, is an essential tool in information security field. In this paper, the residue number system (RNS) is introduced to implement RSA. Based on the design methodology of configurable and scalable processor using transport trigger architecture (TTA), a cryptographic co-processor with high data throughput, low hardware overhead and wide RSA key length range supporting is implemented.Firstly, this paper discusses and optimizes the implementation algorithms of RSA encryption and decryption. An implementation method based on RNS is adopted, and data parallelism of RNS Montgomery modular multiplication algorithm is analyzed. Further more the RNS Montgomery modular multiplication algorithm is re-scheduled according to hardware resource to reveal the maximum data-level parallelism. A particular RNS base, which makes modular multiplication and modular addition operations in the RNS domain simple, is choose to reduce chip area cost. Base on this particular RNS base, an easy implementation transformation method between RNS representation and binary representation is proposed.Secondly, a RSA cryptographic co-processor is designed and the functional units are customized. Some name dependencies are eliminated taking advantage of fine-grained data move of TTA to fully exploit the instruction-level parallelism. A reconfigurable modular multiplication-and-accumulation array is designed to speed up the computation of RNS Montgomery modular multiplication which reduces the bus load and improves the hardware resource utilization. And the interconnections of the co-processor are customized to reduce hardware cost.The result shows that this design achieves high performance. The 1024-bit RSA decryption data throughput is up to 106Kbps at frequency of 100MHZ and the logic is only 101Kgates using SMIC 0.18μm CMOS technology. |
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