FPGA Design And Implementation Of DSP Modules Such As Polarization Demultiplexing In Spatial Coherent Optical Communication Systems

Space optical communication has the advantages of large information capacity,wide communication spectrum,strong directivity of laser beam,small size,low power,strong anti-electromagnetic interference and anti-interception ability,etc.Optical coherent detection technology can effectively improve the sensitivity of the communication system;reduce the complexity of the system,and meet the needs of large-capacity space optical communication systems,respectively.In order to compensate the damage of the signal at the receiving end in the transmission link in real time and improve the data processing rate,it is of great significance to study the real-time DSP algorithm for high-speed spatial coherent optical communication system.This article focuses on real-time algorithms for IQ imbalance,adaptive equalization demultiplexing,and clock synchronization involved in signal demodulation in 2.5 GBaud PM-QPSK coherent receivers.The main research contents are as follows:(1)A low-complexity parallel polarization demultiplexing algorithm for FPGA is proposed.This new algorithm adopts pipeline processing and improves the error accumulation method,which can increase data throughput and reduce hardware implementation complexity.After introducing the principle of the low-complexity parallel polarization demultiplexing algorithm in detail,we make some simulation and analysis for the new algorithm,and analyze the impact of key parameters such as the number of parallel channels,error accumulation method,and step size factor on the performance of the algorithm in detail.After that,the effectiveness of the algorithm is verified.Finally,the FPGA implementation of the algorithm is given.It can be seen from the resource evaluation that the low-complexity parallel polarization demultiplexing algorithm greatly reduces the consumption of hardware resources.(2)Based on the traditional GSOP algorithm,a parallel IQ amplitude equalization algorithm with feedback structure is proposed.And,the effectiveness of the parallel IQ amplitude equalization algorithm is verified by simulation.The development and implementation of the FPGA-based parallel IQ amplitude equalization module is completed.The offline experiment results show that the system bit error rate is zero when the received optical power is-41 dBm.Finally,the resource analysis and clock constraint analysis of the algorithm are carried out.Under the condition of parallelism of 16 and input bit width of 12bit,the algorithm occupies less than one percent of the total resources.The maximum clock frequency that the algorithm can achieve after clock constraint is 357.27 MHz,which can meet our expected requirements of the operating speed of our FPGA chips.(3)The FPGA hardware-algorithm design and implementation of the parallel clock synchronization algorithm is completed,and the feasibility of the clock synchronization module is verified by simulation of the design.