Research And Implementation Of Improved LDPC Decoding Algorithm

In recent years,as there are more and more application scenarios of small unmanned aerial vehicles(UAVs),it's obvious that a higher demand is needed for the reliability and real-time capability of these UAVs'communication links.As one of the key technologies of 5G,Low Density Parity Check(LDPC)codes have the advantages of a simple structure and perfect performance.However,the existing LDPC soft-decision decoding algorithms still have the problem of excessive delay and complexity due to the increase of iteration times,which is difficult to deploy in the UAVs'platform with high real-time requirements and limited resources and size.At the same time,considering the limited resources of small UAVs,it is in line with the current development trend for developing the encoders and decoders suitable for the actual hardware platform.Firstly,on the basis of the basic theory and decoding algorithms of LDPC codes,an improved hybrid-decision decoding algorithm named Bit Flipping Min Sum with Difference to Sum Ratio Factor Based on Unreliable Received Messages(DSR-URMBFMS)is proposed in the thesis.Compared with the traditional Min Sum Algorithm with Difference to Sum Ratio Factor(DSR-MS),the proposed Algorithm combines the advantages of both soft-decision and hard-decision schemes,and locates the correct codewords quickly through information exchange of soft-decision and bit flipping of hard-decision.As a result,the number of major iterations and decoding delay of the algorithm are reduced.The simulation results show that not only the performance can be improved under the proposed algorithm,but also the computational complexity is decreasing due to the reduction of the number of major iterations with it.Secondly,in order to shorten the deployment cycle and combine with the hardware platform that the project relies on,the thesis explores the implementation of a low-complexity LDPC decoder suitable for FPGA using Xilinx's Vivado High Level Synthesis(HLS)tool.For unify loops'boundary and better play advantage in parallel processing of FPGA,a storage structure of expanding the irregular codes as the "regular codes"and compressing is proposed in the thesis.After that,the pipeline or parallel operation of decoding process can be realized by optimizing directives,and the final scheme of decoder selected is output as IP Core for the link call.The synthesis reports show that the decoder can reduce the decoding latency better compared with the serial scheme before optimization.The thesis proposes an improved hybrid-decision decoding algorithm for the application of LDPC codes in the data link system of small UAVs,and explores the possibility to complete the design and implementation of the decoder using Vivado HLS tool,which provides a reference for subsequent experimental research.