Design of high-performance field programmable gate arrays for data intensive applications

In recent years the use of programmable devices has increased in many areas because they have shorter design and production-cycle times and justify lower-volume production than application-specific integrated circuits (ASICs).; Among the many alternatives in programmable devices, Field Programmable Gate Arrays (FPGAs) have shown significant success in recent years because they can provide all the benefits of programmable devices while exceeding the performance of ASICs.; Among the many alternatives in programmable devices, Field Programmable Gate Arrays (FPGAs) have shown significant success in recent years because they can provide all the benefits of programmable devices while exceeding the performance of ASICs.; The unique characteristics of FPGAs, however, raise several issues that need be resolved so steady gains in performance can continue being made for the deep-submicron process technology. The programmability of FPGAs stems from two major blocks: programmable interconnects and programmable logic blocks. The cost and performance of the programmable interconnect worsen as the process technology scales down because wire does not scale as well as logic gates. Thus, the performance of the digital system designed with deep-submicron FPGAs is limited by the interconnect. Another major issue is the small functional capacity of the programmable logic blocks. Attempts to increase the functional capacity of logic blocks have often resulted in a large area penalty due to the rapid increase in the area needed for look-up tables and associated routing resources.; The work presented in this dissertation searches for methods that can solve these problems in three orthogonal domains: circuit, cell-architecture and mapping algorithm. To improve the performance and area of programmable interconnects two power efficient and clock-skew tolerant asynchronous circuit methods are proposed. To increase the performance of arithmetically intensive applications and keep the area penalty small, a coarse-grained dedicated carry architecture is proposed. To improve the performance and reduce the area penalty for the design implementing bit-serial systolic array algorithms, a multi-ported logic block architecture with mapping algorithms is proposed. A combination of the proposed techniques provides a basis for future high-performance FPGAs.