The Research And Implementation Of Convolutional Neural Network Based On FPGA

In recent years,convolutional neural networks have been widely applied in computer vision research.With the increasing number of layers and the increasing size of database,the computing capability of hardware is also demanding.At the same time,with the development of IC technologies,the processing speed and gate density have been increased rapidly.FPGA chips have been integrated with a large number of DSP cores to support the implementation of high-performance multiplication computing,making the FPGA chip particularly suitable for the implementation of highly dense computing in parallel.Therefore,this paper explores the implementation of accelerating convolutional neural network operations based on FPGA platform.The proposed report contains the following parts:Firstly,the performance of accelerating convolutional neural networks is affected by the computational efficiency of each computing unit.Thus the design and optimization of computing unit takes the priority of the proposed system.This paper optimizes and reduces the complexity of network computation by redeveloping the algorithm of convolutional neural network,which can reduce the complex computing module.Through the comparison of the performance of each design,the best performed module of the convolution layer,pooling layer and full-connected layer is selected.Secondly,the topological structure of the convolutional neural network varies by the change of the application scenario.So parameterization of the hardware modules of the networks is also an important problem.According to Verilog HDL code of the convolutional neural network propagation process,this paper uses C++ to write a small package of network middleware,which can be used to generate the whole Verilog HDL code.Finally,since the on-chip resources of FPGA are limited,making full use of the resources to achieve the convolutional neural network computing acceleration is a key issue.This paper analyzes the relationship between the hardware resources and the number of parallel neurons in convolutional layer,pooling layer and full-connected layer through experiments.Then,this paper establishes the mathematical model of the relationship between the minimum forward propagation time of convolutional neural networks and the corresponding number of parallel neurons in each layer through the relationship of resource utilization.In the end,this paper implements the optimal network computing acceleration design in Virtex-7 XC7VX485T chip through the mathematical model,which is better than the previous works.