Research On The First Type Of Short-circuit Characteristics Of SiC MOSFET

As the new wide band gap semiconductor power device,the reliability of Silicon Carbide(SiC)MOSFET under extreme operating conditions has not been fully verified.Due to the smaller chip size and higher current density,the short-circuit(SC)withstand time of SiC MOSFETs is shorter and the SC conditions are more severe compared with Si devices.When multiple chips are used in parallel,due to the mismatch of the chip parameters or circuit parasitic parameters,the electric heating distribution on the chips is uneven,which seriously reduces the SC capability of the power module.Therefore,studying the SC characteristics of SiC MOSFET devices is of great significance for evaluating the SC capability of devices and improving the SC capability of power modules.Firstly,the dispersion of the main device parameters of SiC MOSFET was tested and analyzed.A static characteristic test platform of SiC MOSFET was built by using a power device analyzer.The main device parameters of 30 SiC MOSFET devices produced by the same batch were tested,the variation coefficient and the dispersion of them was calculated and evaluated.Secondly,the effect of device parameters of SiC MOSFET on its SC characteristics was studied.A single-device SC test platform was built.Under the same SC experiment conditions,the SC current and voltage of devices were tested,the SC energy was calculated,and the dispersion of the SC characteristics was evaluated.Then,the basic SC waveforms of SiC MOSFETs were analyzed in combination with the device parameters,and the main device parameters that affect the SC characteristics of SiC MOSFETs were determined and verified through experiments.A device screening method to suppress differences in SC characteristics was proposed and verified under different SC experimental conditions.Finally,the effect mechanism of parasitic inductance on SC characterization of paralleled SiC MOSFETs was clarified.A test platform for SC characteristics of parallel devices was built,the parasitic inductances of initial layout were extracted by Q3D.The effects of multiple parasitic inductance mismatches on SC characterization of paralleled SiC MOSFETs were analyzed by simulation and verified by experiment.The obtained research results can provide a reference for the internal layout of the power modules.