Design And Optimization Of High Short-circuit Withstand SiC MOSFET Devices

SiC is an important third-generation wide-bandgap semiconductor with high thermal conductivity,high mobility,and high breakdown field strength.It has been widely used in electronic power systems,rail transit,new energy vehicles,medical equipment and other fields.SiC MOSFET is regarded as an important substitute for Si IGBT because of its superior performance.However,in terms of short-circuit performance,the performance of SiC MOSFETs has not yet met market expectations.Short-circuit tolerance is one of the important criteria to measure the reliability of SiC MOSFETs.There are a lot of studies to extend the short-circuit tolerance of SiC MOSFETs from the perspective of external circuit protection,but there are few studies to improve the short-circuit tolerance of devices based on the cellular structure.Based on this,this thesis designs and optimizes a 1200 V SiC MOSFET with high short-circuit tolerance from the cellular structure.By establishing a short-circuit simulation model,it can be seen that the point with the highest temperature inside the cell during the short-circuit process is the JFET region,so this research is mainly carried out from the JFET region.First,the width of the JFET region of the SiC MOSFET device is biased.The width of the JFET region is pulled from 1.5 ?m to 4.5 ?m,and the short-circuit tolerance is reduced from 523.3 ?s to 0.83 ?s.At the same time,with the change of the width of the JFET region during the short-circuit process,the change of the peak current of the JFET region inside the cell,the change of the peak current of the channel region,and the change of the on-resistance of the device were studied.On this basis,the figure of merit of short-circuit withstand capability is defined,which reflects the relationship between on-resistance and shortcircuit withstand duration.And it is determined that when the width of the JFET region is 3.1 ?m,the device reaches the optimal value of short-circuit tolerance,and the figure of merit for short-circuit tolerance is 3.64.Next,it is explained that the highest temperature point in the cell structure is the JFET region.The temperature reaches the highest in the JFET region because the electric field strength in the JFET region is the highest.When a certain current flows through the JFET region,the power loss in the JFET region is the largest,so the heat accumulation is faster.When SiC MOSFET is short-circuited,the gate is under strong electric field and high temperature at the same time,and the device is prone to F-N tunneling and hot electron effect.In addition,there are many SiC/Si O2 interface states,so the gate oxide layer is prone to carrier absorption and release.,under sustained shortcircuit stress,the gate short-circuits.Based on the difference between the current path in the short-circuit state and the normal conduction state,a SiC MOSFET with built-in SD structure is proposed.After adding the SD structure,the short-circuit withstand capacity of the device is increased from 12.2 ?s to 14.9 ?s,an increase of 22.1 %;The on-resistance decreased from 3.36m?·cm2 to 3.28m?·cm2,a decrease of 2.4%;the short-circuit withstand figure of merit increased from 3.64 to 4.54,an increase of 24.7%;the peak current in the JEFT area decreased from 35617 A/cm2 to 32265A/cm2,A reduction of 12.2 %;other parameters such as threshold voltage,breakdown voltage,field strength in the JEFT region remain unchanged.Therefore,adding the SD structure can effectively optimize the short-circuit tolerance of the device,and can also reduce the forward conduction resistance of the device and reduce the conduction loss of the device.Finally,the short-circuit withstand capability of SiC MOSFETs of different generations and structures of various companies is compared.