Research On All-digital True Random Number Generator Circuit

The security of communication systems relies heavily on encryption algorithms,and random numbers are the basis for encryption algorithms and are often used to generate key and authentication information.The robustness of the random number generator and the quality of the generated random numbers largely determine the security of the communication system.Considering different application scenarios,this paper implements a true random number generator based on FPGA and ASIC respectively.First,an FPGA-based true random number generator is designed and implemented.Based on the theory of metastable random number generation,a new double NAND gate structure is proposed according to the characteristics of FPGA.Considering the influence of manufacturing process,voltage and temperature on the circuit,the design add the detection of the output sequence module and feeds back module to keep the random number circuit at a suitable bias point,and improve the quality of the random number.The design is based on the Virtex-5 development platform.The random number generation circuit is tested by the NIST random number test suite,with an output rate of 30 Mbps and less resource consumption.Secondly,based on the principle of metastable random number generation,a new random number generation structure is proposed by ASIC design method.The design uses a new type of sense amplifier circuit to make up for slow metastable recovery of the traditional design,and greatly improve the data output rate.In addition,considering of the impact process,voltage and temperature,a new feedback circuit is designed to correct the circuit,and finally improve the robustness of the design.This design uses 0.13 um CMOS technology to achieve.The output rate of 1.9Gbps can be achieved under the conditions of 25? and 1.2V,with good robustness.The circuit simulation results show that this design can meet the requirements of some high performance cryptosystems.