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Study On The Influence Of Wafer Anisotropy On Electrical Parameters Of Devices

Posted on:2021-03-24Degree:MasterType:Thesis
Country:ChinaCandidate:H LiuFull Text:PDF
GTID:2518306104496184Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
In wafer foundry production,a high-performance chip is related to many factors,including: the characteristics of raw materials,the integrity of circuit design,the choice of process,and the quality of the environment and personnel.Compared with others,raw materials play an irreplaceable role,so the requirements for wafers are becoming higher and higher.At present,the raw materials provided by the larger wafer manufacturers in the world can be customized according to customer needs.However,there are some differences in the raw materials produced by various manufacturers.In the actual production process,products produced by different wafer foundries are The nuances of subtle differences are different,which requires careful testing and evaluation of each batch of raw materials.When the experimental wafer was made of CMOS devices,it was found that the resistance value distribution of the devices on the wafer was uneven.From the resistance value distribution chart,it can be seen that Rs(square resistance value)gradually increases from 8 o'clock to 2 o'clock.The uneven distribution of resistance in the medium appears asymmetric,and there is a tendency to increase in a fixed direction,so you can pay attention to some global parameters,such as: camber,curvature,shape,or deviation angle of the central axis.Finally,according to the slicing,it was found that this was because the wafer in question had a large central axis deviation.relevant simulations and experiments are designed to test the influence of the deviation angle of the central axis,and to study the relevant mechanism and solve the problem.This thesis mainly deals with the influence of the anisotropy of the wafer on the characteristics of the transistor,and the physical modeling of the small size effects related to MOSFETs.To improve and solve related problems,the main research work is as follows:1.Analyze the anisotropy of carriers when they are transported inside the crystal by using the single electron approximation theory,combined with carrier scattering mechanism,carrier mobility theory,and effective mass anisotropy,and based on the semiconductor device current formation mechanism Through comprehensive analysis,the relationship between carrier mobility and resistivity is obtained.2.Aiming at the anisotropy of carrier mobility,design simulation experiments,use Sentaurus TCAD software to simulate the mobility under different crystal planes,design a suitable 3D grid and good numerical function methods,which are related to the application of the model.Matching to achieve fast and accurate simulation results,mainly considering lattice vibration scattering,coulomb scattering of ionized impurities,coulomb scattering of interface charges,etc.,as well as doping-dependent models,high-field saturation,and related recombination mechanisms.3.The related experiments are designed to improve the related processes.It is expected that the electrical parameters of the device will reach the expected value.The actual carrier distribution inside the device will be analyzed after the experiment,and reasonable explanations and suggestions will be given in conjunction with related theories.The distribution of doped impurity ions is mainly within the acceptable range by ion implantation.
Keywords/Search Tags:Anisotropy, carrier mobility, device simulation, process improvement, electrical parameters
PDF Full Text Request
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