Research On Key Technologies Of 0.5-15GHz Reconfigurable Ultra-wideband Receiver

With the development of ultra-wideband technology and reconfigurable technology,improvement of silicon-based CMOS process technology's f _Max,and the demand for special application scenarios such as military and anti-terrorism,it has made that silicon-based CMOS technology to be used in the field of RF transceiver.And it has developed and become a research hotspot and research focus of scholars and research institutions.In this paper,we combine the ultra-wideband technology with reconfigurable technology to realize the design of a 0.5-15GHz reconfigurable UWB receiver chip in UMC 28nm CMOS process.Compared with traditional consumer-grade radio frequency integrated circuits(RFICs),the reconfigurable receiver proposed in this paper can support a wider range of applications.In the military,anti-terrorism and other few consumers,high initial research and development costs,and miniaturization application scenarios,the 0.5-15GHz reconfigurable UWB receiver chip proposed in this paper has more application prospects,which can effectively reduce the early development costs and version iterations cost.And it has the advantages of high integration,portable,and configurable communication detection mode.In this paper,we combine ultra-wideband and reconfigurable technology to achieve full-band coverage of 0.5-15GHz through reconfiguration without changing hardware,reducing the time and cost of early development of the RF terminal in special application scenarios.by introducing 0.5-8GHz Ultra-wideband low-noise amplifier and 8-15GHz ultra-wideband low-noise amplifier two channels to achieve 0.5-15GHz full-band reconfigurable.A time domain ADC is introduced as a quantizer in communications or radar receivers,its low power consumption and fast speed features are used to achieve an equivalent time sampling rate of 16Gs/s.The equivalent time sampling and sub-sampling are used to apply the chip for communication and radar,to achieve the integration of communication and detection.And other innovations.The 0.5-15GHz reconfigurable UWB receiver chip proposed in this paper mainly includes0.5-8GHz ultra-wideband low noise amplifier(UWB LNA),8-15GHz UWB LNA,ultra-wideband programmable gain amplifier(UWB PGA),and mixer,high-speed time-domain analog-to-digital converter(TD-ADC)and other modules.Among them,the 0.5-8GHz UWB LNA adopts RC negative feedback method to achieve ultra-wideband impedance matching,and active balun(balance-unbalance)is used to implement single-ended differential conversion.The bandwidth is 7.5GHz,S11 is less than-10d B at interested frequency,the noise figure(NF)is less than 4d B,the gain is greater than 21d B,the K value is greater than 1,and the input third-order intermodulation point(IIP3)is about-10.8307d Bm.The structure of the 8-15GHz UWB LNA is similar to the structure of 0.5-8GHz UWB LNA.The bandwidth is 7GHz,S11 is less than-10d B,noise figure(NF)is less than 4d B,gain is greater than 25d B,K value is greater than 1,and the input third-order intermodulation point(IIP3)is about-12.865d Bm.The UWB PGA uses a two-stage cascaded R-2R resistor load structure to achieve programmable gain.The-3d B bandwidth is greater than 8GHz with an adjustable gain range of 0-24d B,and the adjustment step size is 6d B.The mixer uses the Gilbert multiplication unit structure to achieve the downmixing in the 8-15GHz RF path,reducing the ADC design requirements.After downmixing,the operating bandwidth is greater than 2GHz,the conversion gain is about 5.8d B,and the noise figure(NF)is less than 7d B.The input third-order intermodulation point(IIP3)is about-7d Bm.The maximum NF of the RF front-end circuit for the 0.5-8GHz RF path changes from5.8d B to 4d B as the gain changes from 21d B to 42.5d B;the maximum NF of the RF front-end circuit for the 8-15GHz RF path is basically stable at 11d B as the gain changes from a gain of 26 to 50 and.TD-ADC achieves a maximum sampling rate of 500MHz,the measured signal-to-noise ratio(SNDR)is about 40d B,and the measured spurious-free dynamic range(SFDR)is about 55d B.In this paper,we achieve the design of the reconfigurable receiver chip circuit and layout in the UMC 28nm CMOS process.The area consumption is about 1.01mm²,and the power consumption is about 217.9m W.We implement fabrication of receiver chip proposed in this paper and RF testing.We apply it to QPSK,and 16QAM communication application and use Keysight 89600 VSA to demodulate and get their clear constellation diagrams.Finally,the function and performance of the receiver chip are summarized.The 0.5-15GHz reconfigurable UWB receiver chip proposed in this paper has better comprehensive performance,which can meet the application in military,anti-terrorism and other special portable,small cost scenarios.