Research Of Ultra-Wideband Pulse Radar Receiver Front-End Circuit

With the development of ultra-wideband(UWB)technology,UWB pulse radar has been widely used in the fields of through-the-wall detection,indoor positioning and post-disaster rescue.At the same time,compared with the traditional continuous wave radar,UWB pulse radar has greater advantages in detection accuracy,range resolution and penetration ability.With the development of CMOS process technology,it has been widely used in the design of radio-frequency(RF)integrated circuits after 0.18?m process nodes.With advantages of low power dissipation,high integration and low cost,application fields of UWB pulse radar fabricated in CMOS technology can be expended widely.Besides,UWB pulse radar receiver front-end circuit is the key module of the receiver and further research of it is of great significance.Research status and development trend of UWB pulse radar are introduced firstly in this thesis.Then a novel UWB pulse radar receiver based on equivalent time sampling technique is proposed when the advantages and disadvantages of the existing UWB receiver architectures are compared.RF signal of the receiver is processed directly by the ADC with equivalent time sampling technique,which makes the receiver with advantages of high real-time performance,high precision and low power dissipation.In order to achieve wideband matching,low noise figure and small chip area,a two-stage low noise amplifier(LNA)based on active balun is proposed.Besides,variable gain amplifier(VGA)based on R-2R topology is optimized by level shift technique,which results in greatly improvement of the gain and linearity of the RF front-end circuit.The output buffer inductive resonance technology is used to improve the broadband gain flatness of the RF front-end circuit,and the RF front-end circuit has large bandwidth and high gain.Finally,a low-jitter ring-oscillator phase-locked loop(PLL)is designed to realize equivalent time sampling.The UWB pulse radar receiver front-end circuit and layout are designed using TSMC65nm CMOS process.The RF front-end circuit is under a power supply voltage of 1.8V and a power consumption of 63.3mW.The post-simulation results show that the RF front-end circuit has a S11 of less than-10dB in the frequency range of 1~7GHz,the gain varies from 22.6~46.1dB,and the noise figure varies from 3.16~5.65dB,IIP3 varies from-31.8~-19dBm at the input frequency of 4GHz.The equivalent time sampling circuit is under a power supply voltage of 1.2V and a power consumption of 11.3mW.The equivalent time sampling clock has 32 phases and an equivalent sampling rate of 20 GS/s.The PLL outputs 8-phase clock signals with a resonant frequency of 2.5 GHz,and the post-simulation phase noise(PN)is-107.79dBc/Hz when the PLL output frequency offset is 1MHz.The area of the receiver layout is 1.42mm~2.The simulation analysis shows that the detection distance of the receiver is 4m,the detection time is only 1.6?s,and the detection accuracy is 7.5mm,which satisfies the requirements of UWB pulse radar receiver front-end circuit.