Research And Implementation Of Memory Access Optimization Based On BOOM

In the design process of modern high-performance processors,there are two major issues.One is the computing performance of the processor core,and the other is the efficiency of data interaction between the processor core and the storage system.After decades of development in computer architecture,with the improvement of processor architecture design capabilities and semiconductor manufacturing processes,the performance of processors has almost continuously improved with the speed of Moore's Law.When the computing power of the processor has been greatly improved,the data communication efficiency between the processor and the memory has a critical impact on the performance of the processor and becomes a bottleneck in the overall system.This is what the researchers call storage wall problem.In order to solve the storage wall problem,memory access optimization and cache system design have become an eye-catching and challenging research direction in modern processor design.The BOOM out-of-order superscalar pipeline processor is a general-purpose processor that uses the latest generation of RISCV open source ISA,which uses many classic microarchitecture designs.This article is based on the BOOM processor as a platform for experimentation and optimization.First,it analyzes the architecture characteristics of the superscalar out-of-order pipeline processor and its design ideas,and analyzes the characteristics and optimization space of its memory access unit,cache system,and memory access behavior.Write combining was used as a buffer design idea to reduce the cost of processor accessing memory most of the time.In this article,according to the idea of write combining,cache missing processing and cache accessing,a write combining cache accessing mechanism is added to the cache system's miss processing mechanism.For circuit design part,this article uses a new hardware design language Chisel based on the Scala language,and also uses a series of RISCV tool chain software for development.Secondly,after adding a write combining optimization structure to the cache system,in order to verify the improvement of memory access performance,this article designs a self-contained So C platform bus with a series of IP with hardware resources integrated into it,using the latest Diplomacy bus parameter negotiation and automatic generation design method and an innovative hardware agile development process.Especially after absorbing the features of the Chisel language as a high-level language,the design method brought excellent reusability,scalability,and flexibility to the bus design.As a new chip-level bus interconnect protocol,the Tile Link protocol applied in this paper absorbs the advantages of past bus protocols,has some characteristics suitable for complex systems,and also supports the communication between the cache system and the bus system.Finally,based on the Xilinx vc709 FPGA development board and VIVADO software,the prototype verification system for the BOOM processor platform design was completed with the boot program,and the software and hardware coordination of the Linux system startup on the processor was performed.In addition,we also conducted the SPEC CPU 2006 processor benchmark performance test program.The results show that the write merge optimization scheme designed and implemented in this paper achieves an optimal 2.8% performance improvement on the performance of the BOOM processor platform.According to the results of the DC synthesis tool,the additional hardware overhead,power consumption,and circuit area caused by this optimization mechanism to the cache system are negligible.