Design Of Video Processing Module Based On Spatio-temporal Denoising Algorithm

In today's society,with the continuous advancement of information technology,digital video multimedia technology continues to develop,digital TV display device and system require higher and higher video quality,and video post-processing technology becomes increasingly important.Video denoising technology is an indispensable important technology in video post-processing technology.It can not only improve the quality of video,but also can be used as a pre-processing step for other video enhancement technologies.Therefore,research on video denoising technology has a wide range of engineering application value.Based on the real-time requirement of high-resolution video denoising,the video denoising algorithms based on time domain,space domain and spatio-temporal domain are studied,and the design of ASIC module based on spatio-temporal denoising algorithm is completed,which is regarded as the pre-processing step of the subsequent video processing module.This dissertation first studies the basic theories of digital video denoising from two aspects: noise classification and denoising methods.Then,aiming at the problem of insufficient precision in the implementation of traditional spatio-temporal denoising algorithm,optimization and improvement are made.The optimized contents include dividing the motion intensity into low-pass component and high-pass component for calculation in the motion adaptive time-domain filtering algorithm,penalizing the SAD value in the motion compensation time domain filtering algorithm,determinating the edge points and superposing the high-pass filtered result on low-pass filtered result in the adaptive spatial filtering algorithm.Then,after considering the design factors such as speed,area and power consumption,the design idea of parallel pipeline is used to design and divide the NR module in the ASIC implementation.In order to avoid introducing redundant logic calculations in the hardware design,the input data pre-processing is made into a separate module in the NR module,and after considering the power consumption of the NR module,a clock-gating module is introduced to reduce the clock power consumption.After that,the structural design and logic implementation of each functional sub-module are carried out,including pipeline control module,image boundary calculation module,input data pre-processing module,motion compensation NR module,motion adaptive time domain filtering module and adaptive space domain filtering module.Finally,after the hardware design is completed,this dissertation simulates the DUT on the UVM verification platform,collects the code coverage,analyzes the reason for the low code coverage,and concludes that the low coverage is reasonable.Then,this dissertation tests the NR module of the TV chip after tape-out.Without the original noise-free video sequence,the filtered video sequence is regarded as the ideal video sequence without noise,and the signal-to-noise ratio of the original noisy video sequence is obtained.This signal-to-noise ratio reflects the effect of the hardware design on noise reduction to a certain extent,and proves the functionality of the hardware design.