Design And Verification Of Parameterized On-chip SRAM

With the rapid development of special applications such as large-scale scientific computing has caused people to place extremely high demands on the performance of microprocessors.The development of the IC industry is therefore changing rapidly.As the"engine"of The Digital Signal Processing System,DSP is widely used in signal processing,multimedia and other fields^[1].In order to improve the peak computing efficiency of the DSP,VLIW,SIMD and Pipeline Technology have become important directions for the high-performance DSPs with the goal of fully mining the parallelism of data and instructions.How to provide reliable and high-bandwidth data resources for multiple arithmetic units based on the SIMD architecture,.giving full play to their computing capabilities and improving chip performance has become an important issue in DSP on-chip memory systems.SRAM has the advantages of fast memory access and low power consumption^[2].It is the most commonly used on-chip memory of various embedded processors.This article is based on the design requirements of the high-performance microprocessor architecture independently developed by the National University of Defense Microelectronics.In order to expand its application range,according to the different requirements of different applications and different algorithms for SRAM,the main work is as follows(1)The paper analyzes the functional characteristics of general on-chip SRAM,based on the FT?M-DSP architecture,studies its on-chip scalar and vector memory design specifications and proposes a parametric on-chip SRAM design rules that can provide FT-M-DSP Configurable data access with various granularity such as bandwidth,word width(64bit/32bit),double word,signed halfword with or without,SIMD width(16,8,4,2,1).(2)Based on the analysis of typical applications,the FT?M-DSP on-chip SRAM address calculation process is designed to support two addressing modes.including linear addressing and circular addressing.The on-chip local memory supports instruction shuffle operations of double-word double-access and double-word single-access,it also supports special non-aligned access.A set of fetch instructions supporting multiple addressing modes and fetch granularity is designed,which includes shuffle fetch instructions dedicated to the FFT acceleration algorithm.(3)Adopting high-low bit cross-addressing method,the design realizes low conflict rate,configurable,vector(Load/Store)fetch pipeline and DMA read/write fetch pipeline that support EDAC.(4)Based on a manufacturer's 40nm anti-irradiation process library,the configurable FT?M-DSP on-chip SRAM is compiled and using the typical timing optimization techniques to optimize the path that violates timing to meet the project team's requirements.(5)UVM verification methodologies are used to build a universal hierarchical verification platform.Under the premise of ensuring the completeness and correctness of functional verification,a reference model is written at a higher level.The article used directional incentives and random with constraints to test the correctness of different access modes,improving the accuracy of verification and the efficiency.