The Design And Implementation Of High-Resolution Imaging Radar Simulator

With the rapid development of imaging radar technology,the requirements for imaging radar processors in various industries are becoming higher and higher.First,the acquisition of radar echoes requires a higher sampling rate and resolution.At the same time,the collected echo data must be stored in real time for later analysis and verification of imaging algorithms.Secondly,the imaging radar processor system is required to have higher integration and lighter weight.In some fields,portable is also an important requirement for the system.In addition,in order to improve the development efficiency of imaging radar processors while reducing time and economic costs,the system needs to simulate the generation of radar echoes according to the radar timing.Therefore,developing a high-resolution imaging radar simulator that meets the above-mentioned requirements for imaging radar systems is a subject of great research value.Based on the above requirements for imaging radar systems,a high-resolution imaging radar simulator is designed and implemented in this paper.The main function of the highresolution imaging radar simulator is to simulate the generation of high-resolution radar echoes and to collect and store radar echo data in real time,with multiple functions running in parallel.The simulator system consists of the simulator board and the host.The host serves as the display control and storage platform in the system.The FPGA chip is the most important control core on the board.The data and control signals are transmitted between the board and the host through the PCIe interface.achieve.The radar echo data collected by the ADC chip on the board is transmitted to the host and stored in the hard disk.The imaging algorithm can be verified and researched on the host.After the playback data on the host is transmitted to the board,the FPGA controls the DAC chip for playback,which is used to simulate the radar echo.The acquisition and playback are performed with the radar timing as the trigger signal,and the radar timing parameters can be configured by the host computer.Based on the basic theory of radar principle,analog-to-digital conversion,digital-to-analog conversion,and PCIe interface,this paper proposes a system design scheme based on the system performance index requirements.The design of the entire system is divided into two parts: hardware design and logic code design.Among them,the hardware design part divides the board into six modules: acquisition,playback,clock,PCIe,DDR4 and power supply according to their functions.Chip selection and schematic design are performed according to the system performance indicators.Combining signal integrity analysis theory with PCB layering,layout,and routing technology requirements completes the circuit board PCB design.The main content of the logic code part is the FPGA code design of each functional module,including register parameter design and configuration,AD / DA high-speed data interface parameter design,DDR4 cache logic,and PCIe interface logic.Then,according to the requirements of performance indicators,comprehensively test the function and performance of the system and analyze the test results to ensure the integrity and reliability of the design.At the end of this article,the entire design is summarized,and an improvement plan is proposed for system upgrade and maintenance.