Digital Verification Of 2.4Ghz Narrowband Wireless Communication Transceiver

With the rise of the Internet of Things technology and the advent of the 5G communication era,chips need to meet higher and more complex performance requirements,which brings great challenges to the design work.Small mistakes will cause huge losses,so verification is becoming more and more important.Traditional verification methods have low efficiency and poor reusability,so the costs are high and the verification coverage is insufficient.In recent years,the high-level abstract verification technology represented by System Verilog verification and UVM(Universal Verification Methodology)has effectively improved verification efficiency and greatly reduced labor and time costs.The main work of the thesis is to verify the digital circuit of a narrow-band 2.4Ghz wireless communication transceiver.First,according to the definition and description of the system,the thesis divides the RTL(Register Transfer Level)design of the wireless transceiver in the chip into three parts: the transmitter,the receiver and the frequency synthesizer,and then the functional analysis and verification work are started sequentially.For the transmitter and receiver,the thesis analyzes each functional module such as control state machine,digital modulation,mismatch calibration and digital down conversion in detail,and extracts a complete list of functional test points.Subsequently,based on the analysis and verification goals of functional testing,the thesis determined the verification plan,built a verification platform based on System Verilog,and automatically checked the data flow nodes.In addition,in order to ensure the correct timing in the control circuit,an assertion design is also introduced in the verification scheme.For the digital circuit of the frequency synthesizer,the thesis analyzes the frequency selection and coarse tuning and two-point modulation modules,and gives a detailed list of functional test points and register configurations.At the same time,the thesis combines the preliminary analysis results and actual needs to build a UVM verification platform to check the sub-nodes of each computing module.In addition,a verification component based on the register model has been added to deal with the cumbersome register configuration process.Finally,the thesis combines various functional test points according to the verification plan,constructs test scenarios and completes simulation experiments.The regression test statistics and coverage analysis show that the functional coverage of the entire transceiver digital circuit is 100%,the code coverage of the transmission path is 93.78%,and the code coverage of the frequency synthesizer is 96.4%.