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Design And Implementation Of Synthesized Coverage Monitor

Posted on:2020-12-20Degree:MasterType:Thesis
Country:ChinaCandidate:Y GuoFull Text:PDF
GTID:2428330602951908Subject:Engineering
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With the development of the semiconductor industry,the design scale and complexity of integrated circuits are constantly improving.At present,hundreds of millions of transistors are integrated in a mobile phone baseband chip.In order to fully verify the chip function in a shorter time,function coverage driven verification methodology is widely used in projects.However,different simulation platform in the chip verification flow has different interpretation of the SystemVerilog language,the function coverage which measure the completeness of chip verification can only be used to on the specific simulator platform.The lack of functional coverage measurement on other simulation platforms can lead to risks in the process of manufacturing chips.Currently there is no mature solution for cross-platform function coverage collection and reuse.Based on the research of chip verification methedology and SystemVerilog coverage mechanism,this paper compares DPI(direct programming interface)method which is calling SV built-in method and the method of inserting monitoring module into design to collect function coverage.Finally,the second method was chosen,and a solution with synthesized coverage is proposed.Firstly,based on the research of the built-in function coverage collection mechanism of SystemVerilog language,a general hardware module is designed to monitor the function coverage points in the design.The hardware monitor includes the bin storage area,counters of bin and a global sample module.By configuring the counter width and sampling period,it is possible to balance the accuracy of the coverage data and the impact on the design area or circuit performance.In order to save the time of defining and collecting synthesized coverage in the project,parameter macros,synthesized coverage spec and a monitor code generation system based on Python script and Mako template are defined.The Verifier fills parameters into the synthesized coverage spec,and then the global monitor is generated by the script.Apply the synthesized coverage to the verification of MTM module in project.First,collect and compare the functional coverage and synthesized coverage of the MTM module on simulator,the result is that the two coverage results are very similar.Then check the area of the original MTM module and the new MTM module plugged into the monitor by DC tool.The result show that the MTM design area increased by 2.55% after inserting the 10-digit monitor,and the MTM design area increased by only 0.94% after inserting the 1-digit monitor.This paper designs a synthesized coverage solution which solves the practical problem of cross-platform coverage collection.The solution includes a universal monitor and a tool that can generates the global synthesized coverage monitor code automatically.The synthesized coverage can be used to measure the verification progress on different simulation platforms,and implement reuse from module level to system level and also different simulation platforms.
Keywords/Search Tags:SystemVerilog, function coverage, simulation platform, synthesized coverage monitor
PDF Full Text Request
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