Design And Implementation Of Multi-core SoC Debugging System

With the rapid development of information technology,the data interaction between people,between people and things and between things will be realized in the future through the higher-end Internet and Internet of things technology.Mobile devices such as mobile phones or laptops,as terminals for information transmission,greatly improve the quality of people’s travel.As the core equipment of mobile terminal communication,the multi-core SOC in mobile phone baseband is an important stage for major countries to compete with each other.Since the 1990 s,the manufacturing of integrated circuits has entered into the deep submicron process,and its functional applications have become increasingly complex.People have increasingly high requirements on chip performance,and the traditional single-core SOC has been unable to meet the high frequency communication standards.Therefore,the multi-core SOC has made great progress and become the future development direction of system on chip.Multi-core SOC has powerful functions,a large number of processors,complex work scenarios and long communication links.It not only provides people with high-performance chips,but also brings about an increase in the scale of integrated circuits,which brings great challenges to the debugging of chips.Especially when multiple processors or subsystems need to be debugged cooperatively,the difficulty of locating faults is greatly increased.In order to give full play to the potential of multi-core SOC,it is far from enough to rely on the chip with superior performance.When working,developers need an efficient and convenient debugging system,so as to shorten the development cycle of the chip.In this paper,the debugging system of 5G system in mobile phone baseband SOC is designed,and the synchronization stop mechanism between any processor and any subsystem is realized.The main contents of the work are as follows: firstly,the composition and structure of the whole SOC system are divided,and it is concluded that the system is composed of two types of processors,Xtensa and risc-v.Then,the debugging methods and interfaces of these two processors are studied,and it is concluded that both of them support JTAG debugging and interrupt debugging.However,the debugging system of this multi-core SOC cannot realize the synchronization stop mechanism between any processor and any subsystem,which makes debugging extremely difficult.In order to make up for this defect,a new debugging system should be designed on the basis of the originaldebugging system.In the process of designing the synchronization stop mechanism of the new debugging system,the subsystem list of the multi-core SOC was first divided,and all subsystems were divided into two types according to the composition structure: isomorphic multi-core system and heterogeneous multi-core system.According to the design requirements,the debugging systems for the two types of subsystems were designed respectively.Then it designs the verification process and scheme for the improved debugging system,extracts the function verification points,and designs the function coverage group.At the same time,a verification environment based on joint simulation of UVM and C language was built.Then,based on the extracted functional verification requirements,a large number of test cases were developed and executed to simulate various functions of the debugging system.At the same time,the functional coverage and code coverage reached 100%,and the progress and completeness of the verification work were evaluated.Finally,after the project flow,I cooperated with the software personnel to complete the silicon post-test of various functions of the debugging system,and the test results met the design objectives,proving that the debugging system could be used in the actual work.