The Online Debugging Technology Research In Heterogeneous Multi-Core System

With the rapid development of semiconductor technology and computer technology, the multi-core System-on-Chip(SoC) based on Network-on-Chip(NoC), especially heterogeneous multi-core SoC, has gradually become the mainstream of IC design. Compared to the traditional multi-core systems, the heterogeneous multi-core systems based on NoC have more advantages on power consumption, performance, reliability, and dealing with the complex tasks. At the same time it can realize dynamic allocation of resources and provide strong supports for the parallel multi-thread technology. However, the performance improvement accompanies with more and more difficult chip-debugging tasks. The traditional test methods as well as the pure software debugging means have been unable to ensure the correctness of the hardware design under the condition of limited resources. Fast and effective debugging techniques have become the key to decrease the cost of SoC design.For the above problems, this thesis carries out some researches on the online debugging technology. Paper’s main work is as follows:First of all, this thesis sets up an online tracing model in the service of an completed heterogeneous multi-core system based on NoC, and implements an online debugging architecture. This architecture can trace and output the key information based on the requirements in the process of the system operation, revivify the system working process, support the practical application of the target system, and greatly reduce the debugging time.Secondly, this thesis introduces the design of various modules in the debugging architecture in details, and focus on the studies of the several key modules, including the scheduling algorithm of the tracing data flow among the clusters, the compression of the tracing data and the high-speed output interface. Four scheduling algorithm have been designed to compound the data flow. Combining the run-length coding and LZ77 algorithm, a compression structure adapted to the target system has been implemented. A high-speed transmission interface based on Aurora agreement has also been completedFinally, the performance of the key modules is tested by experiment. The dynamic rotation scheduling algorithm based on threshold and active state judgment has most advantages in resource consumption and overflow ratio; Through the validation of typical tasks, the compression structure can achieve 35% compression ratio; The high-speed output interface can implement 2 Gb/s transmission rate. Besides, three special debug modes are verified and the debugging process is explained through an example, providing support for a variety of debugging requirements of the target system.