The Verification Of HASH Algorithm IP Core Based On UVM

With the continuous development of SOC design scale,IP cores have been widely adopted.The HASH algorithm IP core is widely integrated in the security module of the SOC chip,protecting the information security.With the increasing complexity of the circuit,the difficulty of verification has also greatly increased.As an important part of chip development,verification occupies more than half of the entire SOC R & D cycle.Efficient verification can not only ensure the correct function of the chip,but also improve the efficiency of chip development and reduce costs.With the development of verification technology,the advantages of UVM methodology are gradually reflected.The verification platform based on UVM has high standardization and flexibility,and has become the mainstream verification method today.Based on UVM methodology,this thesis designs a flexible and reliable verification platform for the HASH algorithm IP core in an intelligent voice SOC chip,and comprehensively verifies its functions through dynamic simulation.Firstly,by analyzing the HASH algorithm and the working mode of the module,the verification requirements are determined.Secondly,by analyzing the data interaction between the module and the CPU and DRAM controller,the overall framework of the verification platform is determined,and for each subenvironment,the construction of the components and the connection between them are completed.Among them,according to the external bus interface,the AHB and MBUS bus driver models are established and packaged as sub-environments to improve its reusability;by analyzing the working principle of the algorithm module,the Transaction class is constructed;by studying the principles of HASH algorithms(MD5,SHA1,SHA224,SHA256,SHA384,SHA512,SM3,HMAC,SHA1-PRNG,HASH-DRBG)and the algorithm description library,the algorithm C Model is constructed with C language,and the Reference Model is constructed with System Verilog;by analyzing the data output of the module interface,a monitor is constructed;by constructing transform class,the algorithm comparator is used to construct a scoreboard to complete the automatic comparison of the output results;in order to facilitate the module register access,create a register model for front door access operations.Finally,write random sequences to simulate the actual working scenario of the HASH module.After the completion of the verification platform,test cases are constructed based on the functional test points,and simulation and analysis are performed using EDA tools such as VCS and VERDI to complete the verification of all functional test points.In order to evaluate the completion of verification work,the function coverage model is written and the coverage is collected through multiple regressions.The functional coverage of the module reaches 100%,and the code coverage reaches 97.41%,meeting the expected target.The results show that the verification platform constructed in this thesis can effectively complete the function verification of HASH algorithm IP core.