Design And Verification Of High Speed General External Memory Controller

Since there are still many difficulties in integrating large-capacity memory into the chip,most So Cs will use a large number of external memory chips.The performance of the memory controller will be the key to affecting the system performance.However,the existing universal memory controller has shortcomings in performance and flexibility such as small data throughput and cumbersome sampling settings.Based on the development status of memory controllers at home and abroad,this paper systematically studies the advantages and disadvantages of each controller structure and performance.Focus on optimization and design of the controller's high speed and flexibility,and complete functional verification.The main research work and results are as follows:First of all,a series of optimization design methods are proposed for the controller:(1)According to the transmission characteristics of AXI,a command cache is added inside the AXI module to realize the pipeline of the internal logic of the bus and reduce the transmission behavior of irrelevant logic such as handshake and decoding.The proportion in can improve the utilization rate of bus bandwidth.(2)According to the structural characteristics of the controller,add the data cache between the AXI bus and the arbiter.To a certain extent,the bus communication time can overlaps with the subsequent data processing time and improve the overall transmission performance of the controller.(3)Based on the data sampling characteristics of the memory,this paper proposes a sampling system based on "FIFO-DLLloopback signal",which can compensate for the delay caused by subsequent layout and chip interface devices on the basis of ensuring correct sampling.Then this paper conducts complete software and hardware collaborative verification for the controller.Establish an IP-level verification platform based on the UVM framework for functional integrity verification,and perform So C-level verification for supplemental verification based on an MCU development environment.The verification report shows that the function coverage is 100% and the code coverage is 91%,which can ensure the completeness and achievability of the controller.Under the SMIC40 nanometer process,using Cadence's RTL-Compiler software for synthesis,the clock frequency of the controller can reach the expected value of 200 MHz,the total number of units is 35267,and the unit area is 68553 square microns.Finally,this article also conducts actual tests for a certain MCU equipped with this IP.The test results show that this design can normally complete the communication with the external memory,and can achieve better data transmission effects.In summary,this paper designs a general memory controller based on AMBA AXI,which can improve the memory bandwidth utilization rate and has certain reference significance for the design of other controllers.