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Research On Optimization For High Performance Hardware Transactional Memory In Multicore System

Posted on:2012-06-11Degree:DoctorType:Dissertation
Country:ChinaCandidate:C FuFull Text:PDF
GTID:1118330362950125Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
The emergence of multicore processors shifts single threaded applications to concurrent multithreaded applications easily. Efficiently synchronization between the multicore processors is a key challenge for parallel programming. In the past years, lock mechanisms are used for multithread synchronization. But these systems are error-prone or poor scalability. After many multicore processors appear, Transactional memory is a parallel programming model that is proposed as an alternative to lock-based programming. Transactions allow a thread to execute a sequence of shared memory accesses atomically.Transactional memory can be implemented in hardware, software, or a mixed of the two. Because Software Transactional Memory (STM) systems don't need to modify the existing hardware design, it is very easy to implement. Poor system performance and weak atomicity are two serious disadvantages for most existing STMs. Compared to STM, high performance and strong atomicity of Hardware Transactional Memory (HTM) are very useful advantages for researchers. The most hardware transactional systems can get access to shared memory concurrently. This may lead to data conflicts between transactions and even bring lower system performance or deadlock. Specially, when imperfect signature is used in the real multicore system based on hardware transactional memory, the data conflicts will become more and more. My work is based on this case.The first problem is that the systems use a fixed transaction backoff mechanism without tuning backoff time dynamically. Through monitoring the system runtime information, we proposed an adaptive transaction backoff mechanism with conflict congestion information. This mechanism monitors and records the change of backoff phase and useful transaction phase for tuning backoff time. It is very easy to realize that a transaction backoff time has relationship with the system's conflict information. The system with this mechanism decreases the execution time.The second problem is how to choose a stalled transaction to abort for saving the current work and satisfying requirements of the other waiting transaction. We proposed a transaction abort mechanism based on EnemyQue. It is recored the number of the enemy transactions for every transaction. When the system will abort the stalled transaction and release the occupied resources, it chooses the stalled transaction with the more enemy transactions to abort. This makes more transactions get benefit for its aborting. This mechanism decreases the execution time.The third problem is how to choose transactions to restart. If a transaction restarts without the wanted resource, it has to abort again. So the system will have low performance. We proposed an Alert-on-Update transaction restart mechanism. In this mechanism, after the transaction commit, it will release the occupied resource and alert the enemy transaction to restart and execute. It avoids the restart with blindness and decrease the number of reabort operation. The mechanism also gets performance improvement in EL and LL HTM systems.
Keywords/Search Tags:Multicore Processor, Hardware Transactional Memory, Parallel Programming, Performance Optimization, Transaction Congestion
PDF Full Text Request
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