Designs Of A ADBF Accelerator Based On FPGA

Adaptive Digital Beam Forming(ADBF)is an important branch of array signal processing techniques and widely used in phased array radar,sonar,wireless communication,radio astronomy and many other fields.Because of the splendid electronic anti-jamming capability,ADBF has become a kernel algorithm of active phased array radar signal processing.In recent years,with the rapid development of the integrated circuit industry,digital signal processing dominates the radar design and the field programmable gate array(FPGA)provides a powerful hardware platform for radar implementations.Based on the FPGA platform,this paper presents a high-speed,high-precision and versatile ADBF hardware accelerator,which includes the following IPs:1)A configurable ADBF hardware accelerator:By the dislocation of each pulse and pre-calculation of the difference between the weight,the system efficiency has been greatly improved compared to the traditional design,the throughput is increased by 20%.2)A configurable matrix inverse module:The module uses an improved Cholesky decomposition method to avoid the square root calculations of floating point complex number.At the same time,time-sharing scheduling technology is applied to save the storage and computing resources by about 60%.This module supports the inverse operation of matrices with ant dimension by changing the pre-defined parameters.2)A configurable DBF module:This module implements the beamforming operation of any dimension input by configuring the static parameters,and output the results in serial or parallel according to the different working modes.The joint simulation of MATLAB and MODELSIM proves that the proposed ADBF hardware accelerator works properly can reach a throughput of 100Mbps at the frequency of 200MHz on Xilinx V7-980 board.