Reconfigurable circuits for communication applications and environment-aware receiver

This thesis explores the new applications which benefi t from the exploitation of the digital circuits in the design of RF circuits. Two main applications presented here are the recon figurable circuits design, essential for the design of optimal power consumption receivers and the boost of a circuit's performance beyond its RF-only design limits. The concept of the fi rst environment-aware receiver architecture is introduced for the study of the former application along with a novel, recon figurable, highly linear active mixer. The latter application's practicality is studied through the design of an active phase shifter with improved accuracy regarding its RMS phase and amplitude errors.;The Environment-aware receiver is introduced as a method for achieving an optimal power consumption with the minimum required quality of service of a certain standard. This receiver takes advantage from the use of a channel sensing receiving path to estimate the required phase noise and main linearity merits, IIP3 and P1dB. A novel highly linear, recon figurable mixer with four states of power consumption and linearity is designed based on the dynamic current injection method, introduced in this work. The mixer is a crucial part of the proper adjustment of IIP3 and P1dB of the environment-aware receiver. A set of switches in the LO and IF stage of the mixer help in the achievement of the recon figurable mixer. The dynamic current injection method, used in this design is studied and developed using a pair of cross-coupled pMOS devices. This method improves the linearity of the active mixer without increasing the power consumption or any significant deterioration of other important merits of the mixer.;The accuracy of an active phase shifter is improved beyond its RF-only fundamental limits by the use of a fine passive vector scaling mechanism. While the OTA used in this work introduces large phase gaps and limiting the maximum possible accuracy to 4-bits, the 4-state ne scaling mechanism improves the possible accuracy to 6-bits without increasing the power consumption of the design.