Research And Implementation Of Key Technologies Of Low-power And Low-noise Circuits For Doppler Radar Applications

In recent years,microwave Doppler radar has become more and more widely used as a sensor.Its transceiver circuit design pursues miniaturization,low cost,low power consumption,and high sensitivity.The design of the frequency synthesizer and mixer structure has a significant impact on the above performance.The frequency synthesizer determines the purity of the transmitter’s output spectrum and also affects the demodulation noise of the receiver.The mixer affects the gain,noise,and linearity of the receiver,thereby determining the signal-to-noise ratio at the receiving end.This article is oriented to the application of X-band radar sensors,researches the key circuits in the Doppler radar system,and integrates the above circuits based on the 130nm CMOS process.Firstly,this article introduces the commonly used phase-locked loop structure in frequency synthesizers,and designs a charge pump phase-locked loop according to actual application requirements.The frequency divider circuit is optimized against process and temperature changes to ensure stable operation of the phase-locked loop circuit.The chip has undergone layout design and processing tests.Under the power consumption of 13.05 mW,the chip achieves the frequency lock range of 10.3 GHz-11.3 GHz with the frequency step of 12.5 MHz.The phase noise has the performance of-55.4 dBc/Hz@10kHz,-95.2 dBc/Hz@1MHz,and the spurious power is-35.5 dBc.Secondly,based on the inherent problems of the charge pump phase-locked loop and the results of simulation and testing,in order to further reduce power consumption and optimize output phase noise,this paper designs the structure of a sub-sampling phase-locked loop cascaded by a frequency multiplier optimized for in-band noise.A stacked voltage-controlled oscillator with low power consumption is improved.In order to improve the consistency and stability of performance,this paper uses the loop feedback design method to design oscillator stabilization circuit,duty cycle control circuit,and constant transconductance circuit.This paper has completed the design and simulation of the frequency synthesizer.Under the power consumption of 5.7 mW,the chip achieves the output frequency between 9.6 GHz and 11.4 GHz,the phase noise performance of-126 dBc/Hz@10kHz,-110 dBc/Hz@1MHz,and the integrated RMS jitter is 188 fs.Next,this article studies the mixer structure used in the zero-IF receiver,combined with the time-varying small signal model analysis methods in the literature,to improve the gain and flicker noise model of the single-balanced active mixer.Combined with model analysis,a negative resistance resonant current injection low flicker noise active mixer structure is designed,and the stability of the circuit is enhanced by adding common gate transistors and adjustable components,and adjusting the matching circuit.The performance achieved by the mixer in the post-layout simulation is that under the power consumption of 3 mW,the voltage conversion gain achieves 30dB and the noise figure achieves 9.1dB@10kHz at low-frequency and 6.1dB@100MHz at high-frequency.