Layout conscious approach and bus architecture synthesis for hardware-software co-design of systems on chip optimized for speed and power

This Ph.D. thesis presents a novel hardware/software co-design methodology for SoC, in which task and communication partitioning and scheduling are performed under detailed observation of available hardware resources taking into consideration the dependency between data communication speed and physical design (core placement and bus routing). The methodology permits coarse and medium grained resource sharing across tasks for execution speed up through superior usage of hardware. The hardware/software codesign methodology executes three consecutive steps: (1) It performs combined task partitioning to processor cores, operation binding to functional unit cores, and task and communication scheduling. It also identifies minimum speed constraints for each data communication. (2) The bus architecture is synthesized and buses are routed. IP cores are placed using a hierarchical cluster growth algorithm. Bus architecture synthesis identifies a set of possible building blocks (using the proposed PBS bitwise generation algorithm), then assembles them together using simulated annealing algorithm. Each bus architecture is routed, paracitic extraction is carried out, and bus speeds are characterized. (3) For the best bus architecture, the methodology re-schedules tasks, operations, and communications to minimize system latency. At this step, bus speed accounts for layout parasitic. The thesis also discusses classifications of SoC buses included flat bus, redundant bus and hierarchical bus. Each classification has its synthesis procedure which depends on adaptation of our methodology.; This Ph.D. thesis discusses the use of layout conscious approach designing SoC bus architectures. The limitation is that the BA topology is customized, fixed and used though out the communication processes of IP cores. The cost of design and manufacturing for customized SoC is too high. Therefore, the future direction of this research should address the flexibility of the bus architecture and real-time bus architecture synthesis. The BA should be reconfigurable so that topology can be on-line designed for high performance communication. The SoC integrators friendly connects IP cores together using the architecture at no cost. High performance communication is pursued by real-time synthesis mechanism. This approach closes the gap between performance and cost and is thus attractive to SoC industry. (Abstract shortened by UMI.)...