Development of DCT algorithms with DSP architectures in CAE environments

A digital signal processing design will calculate discrete cosine transforms (DCT) in a hardware simulation environment. The hardware design is a parallel processing architecture which uses digital signal processing chips with pipelining capabilities. It will be demonstrated that the DCT can be performed on 128 x 128 arrays of image data at a rate of twenty frames per second.;The hardware design uses Texas Instruments TMS320C25 digital signal processing chips along with high speed CMOS memory devices. The Computer Aided Engineering workstation which will serve as the platform for the hardware design simulation is the Daisy Megalogician. It will be shown that image processing analysis may be performed with a hardware computer simulation.;The simulation demonstration will show that initial hardware and software analysis with CAE systems is possible for image processing applications. It will also be demonstrated that image display software can be written that will enable image data to be displayed on the same system that performs the hardware simulation. Hardware simulation will show the capability of low cost DSP chips to perform DCTs at video-rates. Furthermore, coding techniques used on the TMS320C25 DSP will be discussed which will reduce the number of instructions required to perform the DCT algorithm.