Multirate signal processing for hardware complexity reduction in digital IC design

Hardware complexity reduction has obvious importance in digital IC design. It can be achieved at several design levels: algorithm, architecture, gate, transistor, and layout. Most approaches have concentrated on the algorithm and architecture levels. The reasons are two-fold: One is that algorithm and architecture designs usually have major impact on the hardware complexity of a digital system. The other reason has to do with automated digital IC design tools; with these tools, a designer does not have to deal with lower levels of design. This dissertation focuses on hardware complexity reduction at these two levels. Instead of working on a specific system, we study certain general hardware complexity issues and develop general techniques. We find, in particular, that multirate signal processing can be employed as a very efficient technique in reducing the hardware complexity of a system. We observe that self-similarity exists in various architectures and algorithms and, based on this observation, with the use of multirate signal processing, we obtain new hardware-efficient architectures and algorithms. We also propose a novel polyphase-signal analysis technique for analyzing a multirate system.; In this dissertation, we consider several specific examples illustrating three aspects of hardware complexity reduction. The first aspect concerns the architecture level, and there we apply multirate signal processing and the polyphase-signal analysis technique to coupled-form IIR filters and lattice FIR filters, yielding hardware-efficient architectures for these two kinds of filters. The second aspect concerns the mapping of an existing algorithm to a hardware architecture. Here, we propose a hardware efficient architecture to implement the adaptive lattice equalization algorithm and an architecture to implement the divide-and-conquer digital squarer algorithm. The third aspect concerns the algorithm level of development. Here, we apply multirate signal processing to a video communication system. More specifically, at the presentation layer of a video communication system, we propose a hardware efficient multistage subsampling motion estimation algorithm. Also, at the physical layer of a communication system, we apply multirate signal processing and the polyphase-signal analysis technique to OFDM, and obtain a hardware efficient OQAM-OFDM transceiver architecture. Finally, an efficient OFDM loading algorithm for bit streams with unequal priority, such as video data streams, is proposed and simulated for communication over a twisted-pair channel.