Wafer Level Reliability for application specific integrated circuits

New semiconductor processes, testing methodologies, and procedures are being developed to increase the amount of reliability assurance testing through Wafer Level Reliability Testing, a new and emerging field. The fundamentals of semiconductor manufacturing processes are presented as a knowledge base required to understand the possible failure mechanisms, test structures, and burn in reliability to understand the application of Wafer Level Reliability Testing to custom Application Specific Integrated Circuits (ASIC) semiconductor devices and its importance to traditional life time reliability testing methodologies. Wafer Level Reliability (WLR) Testing fundamentals involving the fabrication and integration of test structures and production parts on a single wafer, and specific tests for these tests structures, are presented. Empirical test results of traditional life time reliability testing for designed and fabricated wafers containing test structures and ASIC parts are analyzed in detail to determine if there is any correlation between existing process monitor test and the reliability of the product to develop WLR lifetime models. Based on the results, the benefits and limitations of Wafer Level Reliability in controlling manufacturing processes of ASIC semiconductor devices are discussed. (Abstract shortened by UMI.).