Performance driven technology mapping for cell generators

Technology Mapping is the final step in Logic Synthesis and is defined as the transfer of a technology-independent logic network into a circuit realization in a given technology. This thesis discusses the design and implementation of a prototype technology mapper for cell compilers, called Rossini. Issues for the performance optimization of circuits through the utilization of complex cells in a CMOS (Complementary Metal Oxide Semiconductor) technology are addressed. Rossini improves on current mapping techniques by introducing a constraint-driven module whose parameters are defined by the abilities of the cell compiler. This constructive matching technique allows mapping of networks for very large cell families. New partitioning and covering approaches ensure that the mappings are also of high quality. Using this platform for experiment, a study of the impact of different sized cell families is presented. The study shows that larger cell families offer a savings in the area and delay of technology mapped circuits.