Test synthesis of system-level circuits at behavioral and structural domains

Test Synthesis, a term introduced in recent years, refers to both synthesis for testability and traditional design for test (DFT). Originally, synthesis for testability identified gate level optimizations that could preserve or enhance circuit testability for a selected fault class without the need for more specific testability insertion techniques. In this domain, only the removal of combinational redundancies has been widely adopted. However, in the most recent research, more specific testability insertion techniques ranging from ad hoc insertion of control or observe points to insertion of regular structures such as scan chains and built-in self test (BIST) have emerged.; High level test synthesis (HLTS) considers testability during high-level synthesis, with the aim to achieve better testability when compared to DFT at low level. There are two major reasons why high level test synthesis has advantages over DFT at low level: (1) size complexity and (2) functional abstraction. A design grows significantly in size when it is synthesized into a low level description. The second advantage, functional abstraction, allows one to utilize specific functional behaviors, that can be used for various activities during automatic test pattern generation (ATPG).; In this thesis we will show how HLTS can achieve higher testability for BIST oriented test methodologies. Our results show that by considering testability during high-level synthesis, better testability can be obtained when compared to DFT at low level. Our HLTS also allows DFT-like modifications original specification is augmented with some testability features, e.g. extra test points or observability points. In high level synthesis for BIST, it has been shown that some augmentation of the behavioral description can facilitate the BIST-oriented testing of the final design.; This thesis introduces novel techniques for testing system level digital circuits at behavioral and structural domains. Inter-modular test insertions will be utilized to improve controllability as well as observability in a system level circuit. Research results show how inter-modular test insertions to enhance testability, guided by proposed testability analysis technique, result in significantly better fault coverage. Circuit partitioning has been applied to reduce the computation complexity. Moreover, very low hardware overhead has been achieved. This methodology has been successfully applied to test system level circuits to do post-design re-synthesis to improve overall testability. This methodology has achieved 98% and 99% fault coverage level for several different types of system level circuits.; As the shift from RTL synthesis to full-scale leverage of large intellectual property (IP) blocks (cores) continues to gain momentum, design and testing of cores in embedded designs has become more and more popular recently. This thesis presents briefly two approaches to core based designs testing. The first approach is based on a generic model which improves the accessibility of embedded cores and supports core test pattern reuse scheme. This methodology has been applied to industrial designs and achieved very good testing results. The second approach is a proposal of a conceptual model to design testable core-based systems.