| Considerable research effort in the field of microelectronics pushes towards the realization of fully monolithic, chiefly digital, RF transceivers--with the ultimate objective being the implementation of small, inexpensive, low-power communication devices that are robust, testable, and capable of handling multiple communications standards. Two-path zero-IF architectures and single-path bandpass-{dollar}DeltaSigma{dollar}-based architectures strive to attain these dual goals, but neither effectively achieves both.; This thesis proposes a low-IF receiver architecture, which, with modern quadrature image-reject mixers and strategic IF placement, offers a viable solution for realizing digital, monolithic receivers. A critical, and heretofore non-existing, component of such a system--and indeed of any receiver that uses image-reject mixing to alleviate off-chip filtering requirements--is one that efficiently performs bandpass A/D conversion on quadrature signals.; A quadrature variant of a bandpass delta-sigma ({dollar}DeltaSigma{dollar}) modulator is thus proposed, which offers significant theoretical and practical performance advantages over the alternative of a pair of traditional bandpass {dollar}DeltaSigma{dollar} modulators. The design of the transfer functions, systems and circuits needed to realize quadrature {dollar}DeltaSigma{dollar} modulators are explored. Non-ideal effects are examined, interpreted, and combatted.; Unique code-driven layout techniques facilitate the implementation of a fourth-order prototype quadrature bandpass {dollar}DeltaSigma{dollar} modulator in a 0.8-{dollar}mu{dollar}m CMOS process. Clocked at 10 MHz, the IC converts narrow-band 3.75 MHz I and Q inputs, attaining 62-dB maximum SNDR and 67-dB dynamic range--true 10-bit accuracy--in 200-kHz (GSM) bandwidth. Moreover, the IC clearly demonstrates many of the theoretical predictions. Power consumption is 130 mW at 5 V. Die size is 2.4 x 1.8 mm{dollar}sp2{dollar}. |
