| In recent years, many embedded systems have been introduced that require high-performance at a very low cost (e.g., dollar cost, development turn-around time, power consumption, etc.). These systems can be found in consumer products such as digital video and still cameras, cellular telephones and personal communication devices (e.g., digital two-way radios, wireless Internet modems), and digital audio players (e.g., Diamond's Rio MP3 player). Although these applications need high-performance, aggressive general-purpose architectures such as Hewlett-Packard's PA-8500 are too expensive to include in most embedded systems. A better solution is to customize an architecture to the specific performance and cost requirements of an application.; Application-specific integrated processors (ASIPs) have the flexibility to include the minimal instruction set and microarchitecture elements that give good performance and low cost for an application. Because an embedded system often runs a single code (or a small set of codes), an ASIP can be tailored to the requirements of an application to avoid the costly and complex functional devices required by a general-purpose processor for running arbitrary codes. Because cost and time-to-market are very important for embedded systems, an ASIP architecture should permit automatic design, including high-level architectural design. Such an architecture and design system is the focus of this dissertation.; This research uses an application expressed algorithmically in a high-level language as a specification for a processor tailored to the resource and data flow requirements of an application. The target architecture is based on the novel counterflow pipeline (CFP) organization proposed by Sproull, Sutherland, and Molnar. The CFP has several characteristics that make it a good target for the synthesis of application-specific processors: It has a simple and regular structure, local control, high degree of modularity, and inherent handling of complex structures such as register renaming and speculative execution.; In this dissertation, the original counterflow pipeline is extended to a very long instruction word (VLM architecture, called a wide counterflow pipeline (WCFP), that is appropriate for building custom instruction-level parallel processors. Compiler technology is used to derive a WCFP from a highly optimized and software pipelined version of an application's kernel loop. This includes selecting functional devices, determining pipeline stage semantics, and generating the interconnection network for the custom processor (i.e., how pipeline stages and functional units are connected). The system also generates an instruction set architecture for the software pipeline loop. As part of this work, techniques were developed for architecture synthesis, performance analysis, design space exploration, and reconfigurable and fast simulation of counterflow pipelines.; This research demonstrates that counterflow pipelines are appropriate for quickly and automatically constructing application-specific processors. The work shows that custom WCFPs achieve performance competitive with aggressive general-purpose architectures at a low design complexity. This dissertation also shows that WCFPs achieve performance on par with traditional custom VLIWs without requiring expensive and complex global interconnection of functional devices. As part of this research, a framework and design methodology were developed for quickly and easily building a custom pipeline for an embedded application. In the dissertation, we demonstrate that high performance can be obtained from simple pipelines using a straightforward design methodology without resorting to the complex structures found in modern general-purpose architectures. |
