Compatible With Embedded Microcontroller Processor Architecture (m3 Instruction Set Design

In the21th century, with the rapid speed development of SoC(system on chip), the microprocessor, as the SoC core, is acting play more and more important roles in different applications. Embedded processors have extensive application in industrial control, personal consumer electronics, communications, military fields. The most of SoC chips are based on ARM architecture, and ARM’s embedded processors with ARM architecture occupy most of market share in the embedded market.In this dissertation, based on Cortex-M3architecture, an embedded processor is complemented, which is compatible with Cortex-M3instruction set architecture, with high frequency and low power dissipation.First, based on3-stage pipeline of Cortex-M3, to reduce the critical path delay of Execution stage, Execution stage is divided into Execution stage, Memory Access stage and Write Back stage, so the microprocessor’s domain frequency is higher and its performance get improved at the same time.Second, to reduce the power dissipation of the processor, clock gating technology is used in the embedded processorLast, using Harvard bus architecture and2-register write-back mechanism to increase the data throughout, optimize the performance of the pipeline, and simplify design complex of pipeline. For multiply instructions, a3-stsge pipeline hardware multiplier was implemented to increase the system clock frequency, the processor need3cycles to complete one multiply operation. For division instructions, a multi-cycle division algorithm is used to get balance in area and speed.