SOI MOS devices for active matrix electroluminescent displays

Silicon-on-insulator (SOI) technology offers higher speed, lower power consumption, and reduced process complexity as compared to their bulk counterparts. SOI substrates are used in high resolution active matrix electroluminescent (AMEL) displays mainly due to the simple but effective isolation techniques provided by the SOI technology. In this thesis, SOI MOS devices and their specific applications in AMEL displays were investigated.; First, important material parameters such as mobility, minority carrier lifetime, and generation lifetime were determined to investigate the crystalline quality of different types SOI substrates. The high mobility and lifetime values extracted from the experimental results indicate a viable SOI wafer manufacturing technology. Special attention was paid to the design of high voltage lateral double diffused metal oxide semiconductor (LDMOS) transistors used in the AMEL pixel arrays. A two-dimensional simulator was used to model the SOI LDMOS structure and design rules were developed for optimization of the breakdown voltage performance. The design rules were then verified by experimental results from fabricated devices and near ideal breakdown voltage performance of a short drift region LDMOS transistor was demonstrated. The investigation of short drift region devices has led to the successful scaling of the current AMEL pixel technology.; High temperature operation of SOI devices was investigated in detail. It was found that low leakage currents due to the reduced junction area in SOI devices enable them to operate at high temperatures. Comparison of {dollar}rm Isb{lcub}off{rcub}/Isb{lcub}on{rcub}{dollar} ratio at elevated temperatures suggests that dielectrically isolated SOI devices are more suitable for high temperature operations as compared to traditional junction isolated bulk Si transistors. Hot carrier effects, an important reliability hazard for short channel devices, were also studied and it was shown that power-law relationships developed for characterization and lifetime estimation of bulk devices can be extended to partially depleted SOI devices.; Low breakdown voltage of NMOS transistors has been a long known problem in the SOI technology. A possible solution may involve the use of SiGe in the source-drain regions, which lowers the gain of the parasitic bipolar transistor inherent to the SOI NMOS design. The valence band off-set between Si and SiGe leads to an improvement in the breakdown voltage. A two dimensional device simulator was used to demonstrate the feasibility of this concept.