Devices Based On Self-isolation Technology Can Be Integrated Soi High Voltage (> 600v)

The Silicon-on-Insulator (SOI) technology offers low leakage, low power consumption, high speed, low cross-talk and wider safe operating area. It has attracted a lot of attention for use in Power Integrated Circuits (PICs). In PICs, the key technolygies are a high breakdown voltage of Power devices and the effective isolation between the Power devices and the low voltage control circuits.In this thesis a novel high voltage n-channel LDMOS compatible with high-voltage integrated circuit (HVIC) is investigated theoretically and experimentally on the p-type silicon-on-insulator (SOI) layer. The device is characterized by the buried n-islands or the n-layer on buried oxide layer (BOX). According to Possion Equation, the ionized donors in n-islands or the n-layer enhance the bottom-interface electric field of the SOI layer , and thus increases E I, resulting in an enhancement of the breakdown voltage. Compared with the conventional P-type SOI, the breakdown voltage of the implanted n-type drift region on p-type SOI layer is increased from 487V to over 690V. In addition, the self-isolation between the power device and low voltage circuit cell is realized in HVIC, avoiding the dielectric isolation using deep trenches, of which the process is difficult and cost.The influence of structure parameters on the breakdown voltage is discussed by simulation, and the process condition is optimized by the simulator Tsuprem4. A 660V SOI LDMOS in a self-isolation SOI HVIC is realized on a 20μm SOI layer over 4μm BOX. Finally, the software of Tsuprem4 used in process simulation is introduced in this thesis.