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The Research Of The Testability Of Mixed-signal Circuits Based On The DES Theory

Posted on:2004-11-19Degree:MasterType:Thesis
Country:ChinaCandidate:Q B ZhangFull Text:PDF
GTID:2168360092992811Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
With the development of Science and Technology, especially theMicro-electronic technology, the complexities of the circuits have increased. Owing to the analogue nature of many industrial processes and the increasing use of microprocessor techniques, there have been a vast room for the application of mixed-signal (digital and analogue) circuits, and the research for the test on mixed-signal circuit became imminent. The DBS theory that is developed in the recent years gave a systemic method for the mixed-signal circuits test and fault-diagnosis. This paper has researched on the DBS theory's application in the testability of mixed-signal circuit on the basis of the study of DES theory.The main works as follow:(1) We researched the mathematics model of mixed-signal circuits based on the DES theory and it is feasible to deal with the fault diagnosis and the testability of the digital and analog parts in the circuits with an uniform math frame.(2) We programmed a demo's software on Microsoft Visual C++ 6.0 for implementing the algorithms to judge the testability, get the minimum test set and take the fault efficiency of the circuits. The software successfully realizes these functions.(3) We put up the experiments for the faults emulation on some digital signal circuits. These experiments were mainly based on the CPLD/FPGA and we built the testing faulty databases according to these circuits.(4) This paper puts forward a new algorithm based on the Simulated Annealing thoughts for the minimum test set of circuits. This algorithm has tried to ameliorate the weaknesses of the former algorithm based on the greed strategy. Then we discuss some parts of this algorithm in theory.
Keywords/Search Tags:Mixed-signal Circuits, Discrete Event System, Testability, Minimum Test Set, Simulated Annealing
PDF Full Text Request
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