| The thesis proposes design & simulation of a 32-bit 3-1 Interlock Collapsing Arithmetic Logic Unit (ICALU), to allow the execution of two interlocked instructions in a single instruction cycle. This will improve the performance when it is degraded by pipelined hazards. The device will be studied to find out if it meets its objective which is to execute two interlocked instructions in one instruction cycle. The operations will be confined to arithmetic & logical operations on fixed point two's complement numbers. |
