Testing And Diagnosis Of Bridging Faults In Combinational Circuits

With the the rapid development of the IC design and processing technology, the size and the complexity of the circuit system increases sharply. The diagnosis and testing of VLSI has become an increasingly difficult problem. The theory of testing and the technology of design for testability has become an important part in the field of VLSI, and also have very prominent value both in theory and in practice.This paper focus on the bridging faults of the digital circuit, firstly analyzes the characteristics of the bridging faults, as well as the commonly used methods of diagnosis and testing. Then combined with the various of existing theorise of fault simulation, the second section proposed several test generation algorithms for bridging faults diagnosis, along with some optimize methods for test pattern. These algorithms have reduse the size of the test sets and improve the fault coverage obviously.The bridging fault test generation algorithms mentioned in this paper are list as follow: Make use of BDD circuit to generate a complete test set which is called deterministic test generation method; According to the type of the gate in the circuit to determine the value of the primary input which is called pseudo-random test generation method. In addition, here propose a test pattern ordering algorithm to cut down the size of the test set. It is proved that this method can simplify the test set effectively to achieve the optimization purpose. In order to verify the algorithms mentioned above, ISCAS85 testbench are analysisd in the experiments in this paper.Finally, we analyze and summarize the test generation methods for bridging faults in digital circuits presented in this text, and show the effectiveness of these algorithms.